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| MB85RC16 PIN ASSIGNMENT (TOP VIEW) NC 1 8 VDD NC 2 7 WP NC 3 6 SCL VSS 4 5 SDA (FPT-8P-M02) PIN FUNCTIONAL DESCRIPTIONS Pin Number 1 to 3 4 Pin Name NC VSS Unconnected pins Leave it unconnected. Ground pin Serial Data I/O pin This is an I/O pin of serial data for performing bidirectional communication of memory address and writing or reading data. It is possible to connect some devices. It is an open drain output, so a pull-up resistance is required to be connected to the external circuit. Serial Clock pin This is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge. Write Protect pin When Write Protect pin is "H" level, writing operation is disabled. When Write Protect pin is "L" level, the entire memory region can be overwritten. Reading operation is always enabled regardless of the Write Protect pin state. The write protect pin is internally pulled down to VSS pin, and that is recognized as "L" level (the state that writing is enabled) when the pin is the open state. Supply Voltage pin Functional Description 5 SDA 6 SCL 7 WP 8 VDD 2 DS501-00001-2v0-E MB85RC16 BLOCK DIAGRAM Serial/Parallel Converter SDA Memory Address Counter Row Decoder FRAM Array 2,048 x 8 WP Control circuit SCL Column Decoder/Sense Amp/ Write Amp I2C (Inter-Integrated Circuit) The MB85RC16 has the two-wire serial interface and the I2C bus, and operates as a slave device. The I2C bus defines communication roles of "master" and "slave" devices, with the master side holding the authority to initiate control. Furthermore, a I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. * I2C Interface System Configuration Example VDD Pull-up Resistors SCL SDA I2C Bus Master I2C Bus MB85RC16 I2C Bus Other slave DS501-00001-2v0-E 3 MB85RC16 ACKNOWLEDGE (ACK) In the I2C bus, serial data including memory address or memory information is sent in units of 8 bits. The acknowledge signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually outputs the "L" level every time on the 9th SCL clock after every 8 bits are successfully transmitted. On the transmitter side, the bus is temporarily released on this 9th clock to allow the acknowledge signal to be received and checked. During this released period, the receiver side pulls the SDA line down to indicate that the communication works correctly. If the receiver side receives the stop condition before transmitting the acknowledge "L" level, the read operation ends and the I2C bus enters the standby state. If the acknowledge "L" level is not detected, and the Stop condition is not sent, the bus remains in the released state without doing anything. * Acknowledge timing overview diagram SCL 1 2 3 8 9 SDA The transmitter side should always release SDA on the 9th bit. At this time, the receiver side outputs a pull-down if the receive of the previous 8 bit works correctly (ACK response). ACK Start MEMORY ADDRESS STRUCTURE The MB85RC16 has the memory address buffer to store the 11-bit information for the memory address. As for byte write, page write and random read commands, the complete 11-bit memory address is configured by inputting the memory upper address (3 bits) and the memory lower address (8 bits), and saving to the memory address buffer and access to the memory is performed. As for a current address read command, the complete 11-bit memory address is configured by inputting the memory upper address (3 bits) and by the memory address lower 8-bit which has saved in the memory address buffer, and saving to the memory address buffer and access to the memory is performed. DS501-00001-2v0-E 5 MB85RC16 DATA STRUCTURE The master inputs the device address word (8 bits) following the start condition, and then the slave outputs the Acknowledge "L" level on the ninth bit. After confirming the Acknowledge response, the sequential 8-bit memory lower address is input, to the byte write, page write and random read commands. As for the current address read command, inputting the memory lower address is not performed, and the address buffer lower 8-bit is used as the memory lower address. When inputting the memory lower address finishes, the slave outputs the Acknowledge "L" level on the ninth bit again. Afterwards, the input and the output data continue in 8-bit units, and then the Acknowledge "L" level is output for every 8-bit data. * Device Address Word Start SCL 1 2 3 4 5 6 7 8 9 1 2 .. ACK SDA S 1 0 1 0 A2 A1 A0 R/W A .. Access from master Access from slave Device code Memory Upper Address Read/Write code S Start Condition A ACK (SDA is the "L" level) DS501-00001-2v0-E 7 MB85RC16 FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED The MB85RC16 performs the high speed write operations, so any waiting time for an ACK* by the acknowledge polling does not occur. *: In E2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not. It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the start condition and then the device address word (8 bits) during rewriting. WRITE PROTECT (WP) The entire memory array can be write protected by setting the WP pin to the "H" level. When the WP pin is set to the "L" level, the entire memory array will be rewritten. Reading is allowed regardless of the WP pin's "H" level or "L" level. Do not change the WP signal level during the communication period from the start condition to the stop condition. Note : The WP pin is pulled down internally to VSS pin, therefore if the WP pin is open, the pin status is detected as the "L" level (write enabled). 8 DS501-00001-2v0-E MB85RC16 COMMAND * Byte Write If the device address word (R/W "0" input) is sent after the start condition, an ACK responds from the slave. After this ACK, write memory addresses and write data are sent in the same way, and the write ends by generating a stop condition at the end. S 1 0 1 0 A2 A1 A0 0 A Address Low 8bits A Write Data 8bits AP XXX X X X X X X XX Access from master MSB LSB Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) * Page Write If data is continuously sent after the following address when the same command (expect stop condition) as Byte Write was sent, a page write is performed. The memory address rolls over to first memory address (000H) at the end of the address. Therefore, if more than 2 Kbytes are sent, the data is overwritten in order starting from the start of the memory address that was written first. Address Low 8bits Write Data 8bits Write Data S 1 0 1 0 A2 A1 A0 0 A A A ... AP Access from master Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) DS501-00001-2v0-E 9 MB85RC16 * Current Address Read If the last write or read operation finishes correctly up to the end of stop condition, the memory address that was accessed last remains in the memory address buffer (the length is 11 bits). When sending this command without turning the power off, it is possible to read from the memory address n+1 which adds 1 to the total 11-bit memory address n, which consists of the memory upper address 3-bit from the device address word input and the lower 8-bit of the memory address buffer. If the memory address n is the last address, it is possible to read with rolling over to the head of the memory address (000H). The current address (address that the memory address buffer indicates) is undefined immediately after turning the power on. Access from master Access from slave (n+1) memory address S 1 0 1 0 A2 A1 A0 1 A Read Data 8bits NP S Start Condition P Stop Condition A ACK (SDA is the "L"level) N NACK (SDA is the "H" level) * Random Read The one byte of data from the memory address as saved in the memory address buffer can be read out synchronously to SCL by specifying the address in the same way as for a write, and then issuing another start condition and sending the Device Address Word (R/W "1" input). Setting values for the first and the second memory upper address codes should be the same. The final NACK (SDA is the "H" level) is issued by the receiver that receives the data. In this case, this bit is issued by the master side. n address S 1 0 1 0 A2 A1 A0 0 A Address Low 8bits AS 1 0 1 0 A2 A1 A0 1 A Read Data 8bits NP (Input example) when reading memory address 16FH: 001B 01101111B 001B Access from master Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) N NACK (SDA is the "H" level) 10 DS501-00001-2v0-E MB85RC16 * Sequential Read Data can be received continuously following the Device address word (R/W "1" input) after specifying the address in the same way as for Random Read. If the read reaches the end of address for the MB85RC16, the read address automatically rolls over to first memory address (000H). ... A Read Data 8bits A Read Data ... A Read Data 8bits NP Access from master Access from slave P Stop Condition A ACK (SDA is the "L" level) N NACK (SDA is the "H" level) DS501-00001-2v0-E 11 MB85RC16 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage* Input voltage* Output voltage* Ambient temperature Storage temperature Symbol VDD VIN VOUT TA Tstg Rating Min - 0.5 - 0.5 - 0.5 - 40 - 40 Max + 4.0 VDD + 0.5 ( 4.0) VDD + 0.5 ( 4.0) + 85 + 125 Unit V V V C C *: These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage* "H" level input voltage* "L" level input voltage* Ambient temperature Symbol VDD VIH VIL TA Value Min 2.7 VDD x 0.8 - 0.5 - 40 Typ 3.3 Max 3.6 VDD + 0.5 ( 4.0) + 0.6 + 85 Unit V V V C *: These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 12 DS501-00001-2v0-E MB85RC16 ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Input leakage current*1 Output leakage current* 2 Symbol |ILI| |ILO| ICC ISB VOL RIN Condition VIN = 0 V to VDD VOUT = 0 V to VDD SCL = 1 MHz SCL, SDA = VDD WP = 0V or VDD or OPEN TA = + 25 C IOL = 2 mA VIN = VIL (Max) VIN = VIH (Min) Value Min - 50 1 Typ 70 0.1 Max 1 1 100 1 0.4 Unit A A A A V k M Operating power supply current Standby current "L" level output voltage Input resistance for WP pin *1: Applicable pin: SCL,SDA *2: Applicable pin: SDA DS501-00001-2v0-E 13 MB85RC16 2. AC Characteristics (within recommended operating conditions) Value Parameter Symbol STANDARD MODE Min SCL clock frequency Clock high time Clock low time SCL/SDA rise time SCL/SDA fall time Start condition hold Start condition setup SDA input hold SDA input setup SDA output hold Stop condition setup SDA output access after SCL fall Pre-charge time Noise suppression time constant on SCL, SDA Power supply voltage Operating temperature Input voltage amplitude Input rise time Input fall time Input judge level Output judge level : 2.7 V to 3.6 V : - 40 C to + 85 C : 0.3 V to 2.7 V : 5 ns : 5 ns : VDD/2 : VDD/2 FSCL THIGH TLOW Tr Tf THD:STA TSU:STA THD:DAT TSU:DAT TDH:DAT TSU:STO TAA TBUF TSP 0 600 1300 600 600 0 100 0 600 1300 Max 400 300 300 900 50 FAST MODE Min 0 400 600 250 250 0 100 0 250 500 Max 1000 300 100 550 50 kHz ns ns ns ns ns ns ns ns ns ns ns ns ns Unit AC characteristics were measured under the following measurement conditions. 14 DS501-00001-2v0-E MB85RC16 MEMO DS501-00001-2v0-E 19 MB85RC16 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department |
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